xsysctl.c

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//*****************************************************************************
//
//
//*****************************************************************************
#include "xhw_types.h"
#include "xhw_ints.h"
#include "xhw_memmap.h"
#include "xhw_nvic.h"
#include "xhw_sysctl.h"
#include "xdebug.h"
#include "xsysctl.h"
#include "xcore.h"



static unsigned long s_ulExtClockMHz = 12;

//*****************************************************************************
//
// This macro extracts the array index out of the peripheral clock source.
//
//*****************************************************************************
#define SYSCTL_PERIPH_INDEX_CLK(a)                                            \
                                (((a) >> 28) & 0xf)

//*****************************************************************************
//
// This macro constructs the peripheral bit mask from the peripheral clock source.
//
//*****************************************************************************
#define SYSCTL_PERIPH_MASK_CLK(a)                                             \
                                ((((((a) & 0x1f0000) >> 16) <= 20) &&         \
                                ((((a) & 0x1f0000) >> 16) >= 8))  ?           \
                                ((0x7) << ((((a) & 0x1f0000) >> 16))) :       \
                                ((0x3) << ((((a) & 0x1f0000) >> 16))))
//*****************************************************************************
//
// This macro constructs the peripheral bit mask from the clock divder.
//
//*****************************************************************************
#define SYSCTL_PERIPH_MASK_DIV(a)                                             \
                                (((((a) & 0x1f00) >> 8) == 16)?               \
                                ((0xFF) << ((((a) & 0x1f00) >> 8))) :         \
                                ((0xF) << ((((a) & 0x1f00) >> 8))))

//*****************************************************************************
//
// This macro constructs the peripheral enum of the peripheral clock source.
//
//*****************************************************************************
#define SYSCTL_PERIPH_ENUM_CLK(a)                                             \
                                (((a) & 0xff) << (((a) & 0x1f0000) >> 16))
                                
//*****************************************************************************
//
// This macro extracts the array index out of the peripheral number for reset.
//
//*****************************************************************************
#define SYSCTL_PERIPH_INDEX_R(a)(((a) >> 30) & 0x3)

//*****************************************************************************
//
// This macro constructs the peripheral bit mask from the peripheral number for 
// reset.
//
//*****************************************************************************
#define SYSCTL_PERIPH_MASK_R(a) ((a) & 0x20000000) ?                          \
                             (((a) & 0xff0000) >> (((a) & 0x1f000000) >> 24)):\
                             (((a) & 0xff0000) << (((a) & 0x1f000000) >> 24))

//*****************************************************************************
//
// This macro extracts the array index out of the peripheral number for enable.
//
//*****************************************************************************
#define SYSCTL_PERIPH_INDEX_E(a)(((a) >> 14) & 0x3)

//*****************************************************************************
//
// This macro constructs the peripheral bit mask from the peripheral number for 
// enable.
//
//*****************************************************************************
#define SYSCTL_PERIPH_MASK_E(a) ((a) & 0x00002000) ?                          \
                                (((a) & 0xff) >> (((a) & 0x1f00) >> 8)) :     \
                                (((a) & 0xff) << (((a) & 0x1f00) >> 8))

//*****************************************************************************
//
// An array that maps the "peripheral set" number (which is stored in the upper
// nibble of the SYSCTL_PERIPH_* defines) to the GCR_IPRSTC? register that
// controls the software reset for that peripheral.
//
//*****************************************************************************
static const unsigned long g_pulIPRSTRegs[] =
{
    GCR_IPRSTC1,
    GCR_IPRSTC2
};

//*****************************************************************************
//
// An array that maps the "peripheral set" number (which is stored in the upper
// nibble of the SYSCTL_PERIPH_* defines) to the SYSCLK_AHBCLK register that
// controls the run-mode enable for that peripheral.
//
//*****************************************************************************
static const unsigned long g_pulAXBCLKRegs[] =
{
    SYSCLK_AHBCLK,
    SYSCLK_APBCLK
};

//*****************************************************************************
//
// An array that maps the "peripheral clock source set" number (which is stored
// in the upper nibble of the SYSCTL_PERIPH_* defines) to the SYSCLK_CLKSEL? 
// register that set the Clock source for that peripheral.
//
//*****************************************************************************
static const unsigned long g_pulCLKSELRegs[] =
{
    SYSCLK_CLKSEL1,
    SYSCLK_CLKSEL2
};

//*****************************************************************************
//
//
//*****************************************************************************
typedef struct 
{
    unsigned long ulPeripheralBase;
    unsigned long ulPeripheralID;
    unsigned long ulPeripheralIntNum;
}
tPeripheralTable;

//*****************************************************************************
//
//
//*****************************************************************************
static const tPeripheralTable g_pPeripherals[] =
{
    {xGPIO_PORTA_BASE, xSYSCTL_PERIPH_GPIOA, INT_GPAB},
    {xGPIO_PORTB_BASE, xSYSCTL_PERIPH_GPIOB, INT_GPAB},
    {xGPIO_PORTC_BASE, xSYSCTL_PERIPH_GPIOC, INT_GPCDE},
    {xGPIO_PORTD_BASE, xSYSCTL_PERIPH_GPIOD, INT_GPCDE},
    {xGPIO_PORTE_BASE, xSYSCTL_PERIPH_GPIOE, INT_GPCDE},
    {xWDT_BASE,        xSYSCTL_PERIPH_WDOG,  INT_WDT},
    {xUART0_BASE,      xSYSCTL_PERIPH_UART0, INT_UART0},
    {xUART1_BASE,      xSYSCTL_PERIPH_UART1, INT_UART1},
    {xTIMER0_BASE,     xSYSCTL_PERIPH_TIMER0, INT_TIMER0},
    {xTIMER1_BASE,     xSYSCTL_PERIPH_TIMER1, INT_TIMER1},
    {xTIMER2_BASE,     xSYSCTL_PERIPH_TIMER2, INT_TIMER2},
    {xTIMER3_BASE,     xSYSCTL_PERIPH_TIMER3, INT_TIMER3},
    {xSPI0_BASE,       xSYSCTL_PERIPH_SPI0, INT_SPI0},
    {xSPI1_BASE,       xSYSCTL_PERIPH_SPI1, INT_SPI1},
    {xI2C0_BASE,       xSYSCTL_PERIPH_I2C0, INT_I2C0},
    {xPWMA_BASE,       xSYSCTL_PERIPH_PWMA, INT_PWMA},
    {xPWMB_BASE,       xSYSCTL_PERIPH_PWMB, INT_PWMB},
    {xADC0_BASE,       xSYSCTL_PERIPH_ADC0, INT_ADC},
    {xACMP0_BASE,      xSYSCTL_PERIPH_ACMP0,INT_ACMP},
    {0,                0,                   0},
};
    
                                
//*****************************************************************************
//
//
//*****************************************************************************
#if defined(gcc) || defined(__GNUC__)
void __attribute__((naked))
SysCtlDelay(unsigned long ulCount)
{
    __asm("    sub     r0, #1\n"
          "    bne     SysCtlDelay\n"
          "    bx      lr");
}
#endif
#if defined(ewarm) || defined(__ICCARM__)
void
SysCtlDelay(unsigned long ulCount)
{
    __asm("    subs    r0, #1\n"
          "    bne.n   SysCtlDelay\n"
          "    bx      lr");
}
#endif
#if defined(rvmdk) || defined(__CC_ARM)
__asm void
SysCtlDelay(unsigned long ulCount)
{
    subs    r0, #1;
    bne     SysCtlDelay;
    bx      lr;
}
#endif

//*****************************************************************************
//
//
//*****************************************************************************
#ifdef xDEBUG
static xtBoolean
SysCtlPeripheralValid(unsigned long ulPeripheral)
{
    return((ulPeripheral == SYSCTL_PERIPH_ISP) ||
           (ulPeripheral == SYSCTL_PERIPH_WDT) ||
           (ulPeripheral == SYSCTL_PERIPH_GPIO)||
           (ulPeripheral == SYSCTL_PERIPH_TMR0)||
           (ulPeripheral == SYSCTL_PERIPH_TMR1)||
           (ulPeripheral == SYSCTL_PERIPH_TMR2)||
           (ulPeripheral == SYSCTL_PERIPH_TMR3)||
           (ulPeripheral == SYSCTL_PERIPH_I2C0)||
           (ulPeripheral == SYSCTL_PERIPH_SPI0)||
           (ulPeripheral == SYSCTL_PERIPH_SPI1)||
           (ulPeripheral == SYSCTL_PERIPH_UART0) ||
           (ulPeripheral == SYSCTL_PERIPH_UART1) ||
           (ulPeripheral == SYSCTL_PERIPH_PWM01) ||
           (ulPeripheral == SYSCTL_PERIPH_PWM23) ||
           (ulPeripheral == SYSCTL_PERIPH_PWM45) ||
           (ulPeripheral == SYSCTL_PERIPH_PWM67) ||
           (ulPeripheral == SYSCTL_PERIPH_ADC) ||
           (ulPeripheral == SYSCTL_PERIPH_ACMP));
}
#endif

//*****************************************************************************
//
//
//*****************************************************************************
void
xSysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig)
{
    unsigned long ulOscFreq, ulSysDiv;
    unsigned long ulNF, ulNR, ulNO;
    xASSERT((ulSysClk > 0 && ulSysClk <= 50000000));

    //
    // Calc oscillator freq
    //
    s_ulExtClockMHz = ((ulConfig & SYSCTL_XTAL_MASK) >> 8);
    SysCtlKeyAddrUnlock();
    
    switch(ulConfig & SYSCTL_OSCSRC_M)
    {
        case xSYSCTL_OSC_MAIN:
        {
            xASSERT(!(ulConfig & xSYSCTL_MAIN_OSC_DIS));
            
            xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_XTL12M_EN;
            
            SysCtlHClockSourceSet(SYSCTL_HLCK_S_EXT12M);
            //
            // Wait for the External 4~24 MHz High Speed Crystal Clock Source is stable
            //
            while(!(xHWREG(SYSCLK_CLKSTATUS) & SYSCLK_CLKSTATUS_XTL12M_STB));
            ulOscFreq = s_ulExtClockMHz*1000000;      
            if((ulConfig & SYSCLK_PWRCON_OSC22M_EN)!=0)
            {
                xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_OSC22M_EN;
            }
            if((ulConfig & SYSCLK_PLLCON_PD)!=0)
            {
                xHWREG(SYSCLK_PLLCON) |= SYSCLK_PLLCON_PD;
            }
            break;
        }

        case xSYSCTL_OSC_INT:
        {
            xASSERT(!(ulConfig & xSYSCTL_INT_OSC_DIS));  
            xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_OSC22M_EN;
            SysCtlHClockSourceSet(SYSCTL_HLCK_S_INT22M);
            //
            // Wait for Internal 22.1184 MHz High Speed Oscillator Clock Source is stable
            //
            while(!(xHWREG(SYSCLK_CLKSTATUS) & SYSCLK_CLKSTATUS_OSC22M_STB));
            ulOscFreq = 22000000;
            if((ulConfig & SYSCLK_PWRCON_XTL12M_EN)!=0)
            {
                xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_XTL12M_EN;
            }
            if((ulConfig & SYSCLK_PLLCON_PD)!=0)
            {
                xHWREG(SYSCLK_PLLCON) |= SYSCLK_PLLCON_PD;
            }
            break;
        }
        case xSYSCTL_OSC_INTSL:
        {
            ulOscFreq = 10000;
            xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_OSC10K_EN;
            SysCtlHClockSourceSet(SYSCTL_HLCK_S_INT10K);
            //
            // Wait for Internal 10 kHz Low Speed Oscillator Clock Source is stable
            //
            while(!(xHWREG(SYSCLK_CLKSTATUS) & SYSCLK_CLKSTATUS_OSC10K_STB));
            if((ulConfig & SYSCLK_PWRCON_OSC22M_EN)!=0)
            {
                xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_OSC22M_EN;
            }
            if((ulConfig & SYSCLK_PWRCON_XTL12M_EN)!=0)
            {
                xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_XTL12M_EN;
            }
            if((ulConfig & SYSCLK_PLLCON_PD)!=0)
            {
                xHWREG(SYSCLK_PLLCON) |= SYSCLK_PLLCON_PD;
            }
            break;
        }
        default:
        {
            xASSERT(0);
            break;
        }
                
    }
    if(ulSysClk == ulOscFreq)
    {
        SysCtlIPClockDividerSet(SYSCTL_PERIPH_HCLK_D | (SYSCTL_SYSDIV_1 + 1));
    }
    else if (ulSysClk <= ulOscFreq)
    {
        //
        // Calc the SysDiv
        //    
        xASSERT(ulSysClk <= ulOscFreq);
            
        for(ulSysDiv = 1; ulSysDiv < 16; ulSysDiv++)
        {
            if((ulOscFreq / (ulSysDiv + 1)) <= ulSysClk)
            {
                break;
            }
        }
        xASSERT(ulSysDiv < 16);
        SysCtlIPClockDividerSet(SYSCTL_PERIPH_HCLK_D | (ulSysDiv + 1));
    }
    else
    {
        xASSERT(!(ulConfig & xSYSCTL_PLL_PWRDN));
        xASSERT((ulSysClk >= 25000000 && ulSysClk <= 50000000));
        xASSERT(((ulConfig & SYSCTL_OSCSRC_M) == xSYSCTL_OSC_MAIN) ||
                ((ulConfig & SYSCTL_OSCSRC_M) == xSYSCTL_OSC_INT));
        ulSysClk = ulSysClk << 2;
        ulNF = ulSysClk/1000000;
        ulNR = ulOscFreq/1000000;
        ulNO = 0x3;
        if((ulConfig & SYSCLK_PLLCON_PLL_SRC)==0)
        {
            //
            // Check the arguments .
            //
            xASSERT((ulConfig & SYSCLK_PWRCON_XTL12M_EN)==0); 
            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_PLL_SRC;
            if(ulNR%4 == 0)
            {
                ulNF >>= 2;
                ulNR >>= 2;
            }
            else if(ulNR%2 == 0)
            {
                ulNF >>= 1;
                ulNR >>= 1;
            }    
            else 
            {
                if(ulSysClk % ulOscFreq == 0)
                {
                    ulNR = ulOscFreq/1000000/2;
                    ulNF = ulSysClk*ulNR/ulOscFreq;
                }
                else
                xASSERT(0);
            }
        }
        else 
        {
            //
            // Check the arguments .
            //
            xASSERT((ulConfig & SYSCLK_PWRCON_OSC22M_EN)==0);   
            xHWREG(SYSCLK_PLLCON) |= SYSCLK_PLLCON_PLL_SRC;
            ulNF >>= 1;
            ulNR >>= 1;
            if((ulConfig & SYSCLK_PWRCON_XTL12M_EN)!=0)
            {
                xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_XTL12M_EN;
            }
        }
        xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_OSC22M_EN;
        SysCtlHClockSourceSet(SYSCTL_HLCK_S_INT22M);
        xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_FB_DV_M;
        xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_IN_DV_M;
        xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_OUT_DV_M;
        xHWREG(SYSCLK_PLLCON) |= ((ulNF-2) << SYSCLK_PLLCON_FB_DV_S);
        xHWREG(SYSCLK_PLLCON) |= ((ulNR-2) << SYSCLK_PLLCON_IN_DV_S);
        xHWREG(SYSCLK_PLLCON) |= (ulNO << SYSCLK_PLLCON_OUT_DV_S);
        xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_OE;
        xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_PD;
        SysCtlDelay(1000);
        SysCtlHClockSourceSet(SYSCTL_HLCK_S_PLL);
        //
        // Wait for Internal PLL Clock Source is stable
        //
        while(!(xHWREG(SYSCLK_CLKSTATUS) & 0x00000004));
        SysCtlIPClockDividerSet(SYSCTL_PERIPH_HCLK_D | (SYSCTL_SYSDIV_1 + 1));
        if((ulConfig & SYSCLK_PWRCON_OSC22M_EN)!=0)
                {
                        xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_OSC22M_EN;
                }
    }
    SysCtlKeyAddrLock();
}
        
//*****************************************************************************
//
//
//*****************************************************************************
void 
xSysCtlPeripheralEnable2(unsigned long ulPeripheralBase)
{
    unsigned long i;
    for(i=0; g_pPeripherals[i].ulPeripheralBase != 0; i++)
    {
        if(ulPeripheralBase == g_pPeripherals[i].ulPeripheralBase)
        {
            SysCtlPeripheralEnable(g_pPeripherals[i].ulPeripheralID);
            break;
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
xSysCtlPeripheralDisable2(unsigned long ulPeripheralBase)
{
    unsigned long i;
    for(i=0; g_pPeripherals[i].ulPeripheralBase != 0; i++)
    {
        if(ulPeripheralBase == g_pPeripherals[i].ulPeripheralBase)
        {
            SysCtlPeripheralDisable(g_pPeripherals[i].ulPeripheralID);
            break;
        }
    }
}
        
//*****************************************************************************
//
//
//*****************************************************************************
void 
xSysCtlPeripheralReset2(unsigned long ulPeripheralBase)
{
    unsigned long i;
    for(i=0; g_pPeripherals[i].ulPeripheralBase != 0; i++)
    {
        if(ulPeripheralBase == g_pPeripherals[i].ulPeripheralBase)
        {
            SysCtlPeripheralReset(g_pPeripherals[i].ulPeripheralID);
            break;
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
unsigned long 
xSysCtlPeripheralIntNumGet(unsigned long ulPeripheralBase)
{
    unsigned long i;
    
    //
    // Check the arguments.
    //
    xASSERT((ulPeripheralBase == xGPIO_PORTA_BASE)||
            (ulPeripheralBase == xGPIO_PORTB_BASE)||
            (ulPeripheralBase == xGPIO_PORTC_BASE)||
            (ulPeripheralBase == xGPIO_PORTD_BASE)||
            (ulPeripheralBase == xGPIO_PORTE_BASE)||
            (ulPeripheralBase == xWDT_BASE)||   
            (ulPeripheralBase == xUART0_BASE)||   
            (ulPeripheralBase == xUART1_BASE)||   
            (ulPeripheralBase == xTIMER0_BASE)||    
            (ulPeripheralBase == xTIMER1_BASE)||          
            (ulPeripheralBase == xTIMER2_BASE)||    
            (ulPeripheralBase == xTIMER3_BASE)||        
            (ulPeripheralBase == xSPI0_BASE)||     
            (ulPeripheralBase == xSPI1_BASE)||
            (ulPeripheralBase == xI2C0_BASE)||   
            (ulPeripheralBase == xPWMA_BASE)||
            (ulPeripheralBase == xPWMB_BASE)||
            (ulPeripheralBase == xACMP0_BASE)||
            (ulPeripheralBase == xADC0_BASE)
            );
            
    for(i=0; g_pPeripherals[i].ulPeripheralBase != 0; i++)
    {
        if(ulPeripheralBase == g_pPeripherals[i].ulPeripheralBase)
        {
            break;
        }
    }
    return g_pPeripherals[i].ulPeripheralIntNum;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
xSysCtlPeripheralClockSourceSet(unsigned long ulPeripheralSrc,
                                unsigned long ulDivide)
{
    //
    // Check the arguments. 
    //
    xASSERT((ulPeripheralSrc==xSYSCTL_WDT0_HCLK_2048)||
            (ulPeripheralSrc==xSYSCTL_WDT0_EXTSL)||
            (ulPeripheralSrc==xSYSCTL_WDT0_INTSL)||
            (ulPeripheralSrc==xSYSCTL_ADC0_MAIN)||
            (ulPeripheralSrc==xSYSCTL_ADC0_PLL) ||
            (ulPeripheralSrc==xSYSCTL_ADC0_HCLK)||
            (ulPeripheralSrc==xSYSCTL_ADC0_INT) ||
            (ulPeripheralSrc==xSYSCTL_TIMER0_MAIN)||
            (ulPeripheralSrc==xSYSCTL_TIMER0_HCLK)||
            (ulPeripheralSrc==xSYSCTL_TIMER0_INT) ||
            (ulPeripheralSrc==xSYSCTL_TIMER1_MAIN)||
            (ulPeripheralSrc==xSYSCTL_TIMER1_HCLK)||
            (ulPeripheralSrc==xSYSCTL_TIMER1_INT) ||
            (ulPeripheralSrc==xSYSCTL_TIMER2_MAIN)||
            (ulPeripheralSrc==xSYSCTL_TIMER2_HCLK)||
            (ulPeripheralSrc==xSYSCTL_TIMER2_INT) ||
            (ulPeripheralSrc==xSYSCTL_TIMER3_MAIN)||
            (ulPeripheralSrc==xSYSCTL_TIMER3_HCLK)||
            (ulPeripheralSrc==xSYSCTL_TIMER3_INT)||
            (ulPeripheralSrc==xSYSCTL_UART0_MAIN)||
            (ulPeripheralSrc==xSYSCTL_UART0_PLL)||
            (ulPeripheralSrc==xSYSCTL_UART0_INT)||
            (ulPeripheralSrc==xSYSCTL_PWMA_MAIN)||
            (ulPeripheralSrc==xSYSCTL_PWMA_HCLK)||
            (ulPeripheralSrc==xSYSCTL_PWMA_INT) ||
            (ulPeripheralSrc==xSYSCTL_PWMB_MAIN)||
            (ulPeripheralSrc==xSYSCTL_PWMB_HCLK)||
            (ulPeripheralSrc==xSYSCTL_PWMB_INT) ||
            (ulPeripheralSrc==xSYSCTL_FRQDIV_MAIN)||
            (ulPeripheralSrc==xSYSCTL_FRQDIV_HCLK)||
            (ulPeripheralSrc==xSYSCTL_FRQDIV_INT) 
           );
    xASSERT((ulDivide <= 256) && (ulDivide >= 1));

    //
    // Set the peripheral clock source
    //
    SysCtlKeyAddrUnlock();
    
    xHWREG(g_pulCLKSELRegs[SYSCTL_PERIPH_INDEX_CLK(ulPeripheralSrc)]) &=
        ~(SYSCTL_PERIPH_MASK_CLK(ulPeripheralSrc));
    xHWREG(g_pulCLKSELRegs[SYSCTL_PERIPH_INDEX_CLK(ulPeripheralSrc)]) |=
        SYSCTL_PERIPH_ENUM_CLK(ulPeripheralSrc);
    
    if (ulPeripheralSrc & 0x01000000)
    {
        xHWREG(SYSCLK_CLKDIV) &= ~(SYSCTL_PERIPH_MASK_DIV(ulPeripheralSrc));
        xHWREG(SYSCLK_CLKDIV) |= ((ulDivide-1) << (((ulPeripheralSrc) & 
                                  0x1f00) >> 8));
    }
    SysCtlKeyAddrLock();
}


//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlPeripheralReset(unsigned long ulPeripheral)
{
    volatile unsigned long ulDelay;

    //
    // Check the arguments.
    //
    xASSERT(SysCtlPeripheralValid(ulPeripheral));

    //
    // Put the peripheral into the reset state.
    //
    xHWREG(g_pulIPRSTRegs[SYSCTL_PERIPH_INDEX_R(ulPeripheral)]) |=
        SYSCTL_PERIPH_MASK_R(ulPeripheral);

    //
    // Delay for a little bit.
    //
    for(ulDelay = 0; ulDelay < 16; ulDelay++)
    {
    }

    //
    // Take the peripheral out of the reset state.
    //
    xHWREG(g_pulIPRSTRegs[SYSCTL_PERIPH_INDEX_R(ulPeripheral)]) &=
        ~(SYSCTL_PERIPH_MASK_R(ulPeripheral));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlPeripheralEnable(unsigned long ulPeripheral)
{
    //
    // Check the arguments.
    //
    xASSERT(SysCtlPeripheralValid(ulPeripheral));

    //
    // Enable this peripheral.
    //
    SysCtlKeyAddrUnlock();
    xHWREG(g_pulAXBCLKRegs[SYSCTL_PERIPH_INDEX_E(ulPeripheral)]) |=
                                            SYSCTL_PERIPH_MASK_E(ulPeripheral);
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlPeripheralDisable(unsigned long ulPeripheral)
{
    //
    // Check the arguments.
    //
    xASSERT(SysCtlPeripheralValid(ulPeripheral));

    //
    // Disable this peripheral.
    //
    SysCtlKeyAddrUnlock();
    xHWREG(g_pulAXBCLKRegs[SYSCTL_PERIPH_INDEX_E(ulPeripheral)]) &=
                                          ~(SYSCTL_PERIPH_MASK_E(ulPeripheral));
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlReset(void)
{
    //
    // Perform a software reset request.  This will cause the device to reset,
    // no further code will be executed.
    //
    xHWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;

    //
    // The device should have reset, so this should never be reached.  Just in
    // case, loop forever.
    //
    while(1)
    {
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlSleep(void)
{
    //
    // Wait for an interrupt to wake up.
    //
    SysCtlPowerDownEnable(1);
    SysCtlPowerDownWaitCPUSet(1);
    xCPUwfi();
    SysCtlPowerDownEnable(0);
    SysCtlPowerDownWaitCPUSet(0);

}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlDeepSleep(void)
{
    //
    // Enable deep-sleep.
    //
    xHWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
    SysCtlPowerDownEnable(1);
    SysCtlPowerDownWaitCPUSet(1);

    //
    // Wait for an interrupt.
    //
    xCPUwfi();

    //
    // Disable deep-sleep so that a future sleep will work correctly.
    //
    xHWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
    SysCtlPowerDownEnable(0);
    SysCtlPowerDownWaitCPUSet(0);
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlPowerDownWaitCPUSet(xtBoolean bEnable)
{    
    //
    // Enable BOD reset function or interrupt function.
    //
    SysCtlKeyAddrUnlock();
    if(bEnable)
    {
        xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_PD_WAIT_CPU;
    }
    else
    {
        xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_PD_WAIT_CPU;
    }
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlPeripheralClockSourceSet(unsigned long ulPeripheralSrc)
{
    //
    // Check the arguments.  
    //
    xASSERT((ulPeripheralSrc==SYSCTL_PERIPH_WDG_S_HCLK_2048) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_WDG_EXTSL) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_WDG_S_INT10K) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_ADC_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_ADC_S_PLL) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_ADC_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_ADC_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR0_S_EXT12M)||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR0_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR0_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR1_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR1_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR1_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR2_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR2_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR2_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR3_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR3_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_TMR3_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_UART_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_UART_S_PLL) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_UART_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM01_S_EXT12M)||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM01_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM01_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM23_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM23_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM23_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM45_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM45_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM45_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM67_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM67_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_PWM67_S_INT22M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_FRQDIV_S_EXT12M) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_FRQDIV_S_HCLK) ||
            (ulPeripheralSrc==SYSCTL_PERIPH_FRQDIV_S_INT22M)                   
           );

    //
    // Set  this peripheral clock source
    //
    SysCtlKeyAddrUnlock();
    xHWREG(g_pulCLKSELRegs[SYSCTL_PERIPH_INDEX_CLK(ulPeripheralSrc)]) &=
        ~(SYSCTL_PERIPH_MASK_CLK(ulPeripheralSrc));
    xHWREG(g_pulCLKSELRegs[SYSCTL_PERIPH_INDEX_CLK(ulPeripheralSrc)]) |=
        SYSCTL_PERIPH_ENUM_CLK(ulPeripheralSrc);
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlHClockSourceSet(unsigned long ulHclkSrcSel)
{
    //
    // Check the arguments.
    //
    xASSERT(((ulHclkSrcSel==SYSCTL_HLCK_S_EXT12M)?
              (xHWREG(SYSCLK_PWRCON) & SYSCLK_PWRCON_XTL12M_EN)
              == SYSCLK_PWRCON_XTL12M_EN
          : 1)||
            ((ulHclkSrcSel==SYSCTL_HLCK_S_PLL)?
             (xHWREG(SYSCLK_PLLCON)&SYSCLK_PLLCON_OE)==0 &&
             (xHWREG(SYSCLK_PLLCON)&SYSCLK_PLLCON_PD)==0
          : 1)||
            ((ulHclkSrcSel==SYSCTL_HLCK_S_INT10K)?
             (xHWREG(SYSCLK_PWRCON) & SYSCLK_PWRCON_OSC10K_EN)
             == SYSCLK_PWRCON_OSC10K_EN
          : 1)||
            ((ulHclkSrcSel==SYSCTL_HLCK_S_INT22M)?
             (xHWREG(SYSCLK_PWRCON) & SYSCLK_PWRCON_OSC22M_EN)
             == SYSCLK_PWRCON_OSC22M_EN
          : 1)
           );

    //
    // Enable HCLK clock source.
    //
    SysCtlKeyAddrUnlock();
    xHWREG(SYSCLK_CLKSEL0) &=~SYSCLK_CLKSEL0_HCLK_M;
    xHWREG(SYSCLK_CLKSEL0) |=ulHclkSrcSel;
    SysCtlKeyAddrLock();
}


//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlSysTickSourceSet(unsigned long ulHclkSrcSel)
{
    //
    // Check the arguments.
    //
    xASSERT((ulHclkSrcSel==SYSCTL_STCLK_S_EXT12M)||
            (ulHclkSrcSel==SYSCTL_STCLK_S_EXT12M_2)||
            (ulHclkSrcSel==SYSCTL_STCLK_S_HCLK_2)||
            (ulHclkSrcSel==SYSCTL_STCLK_S_INT22M_2)
           );

    //
    // Enable SysTickclock source.
    //
    SysCtlKeyAddrUnlock();
    xHWREG(SYSCLK_CLKSEL0) &=~SYSCLK_CLKSEL0_STCLK_M;
    xHWREG(SYSCLK_CLKSEL0) |=ulHclkSrcSel;
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlCPUReset(void)
{
    SysCtlKeyAddrUnlock();
    xHWREG(GCR_IPRSTC1) |= GCR_IPRSTC1_CPU;
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlChipReset(void)
{
    SysCtlKeyAddrUnlock();
    xHWREG(GCR_IPRSTC1) |= GCR_IPRSTC1_CHIP;
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
xtBoolean 
SysCtlKeyAddrUnlock(void)
{
    //
    // Unlock the protected registers.
    //
    xHWREG(GCR_REGLOCK) = 0x59;
    xHWREG(GCR_REGLOCK) = 0x16;
    xHWREG(GCR_REGLOCK) = 0x88;
    
    return xHWREG(GCR_REGLOCK)&0x01;
}

//*****************************************************************************
//
//
//*****************************************************************************
xtBoolean 
SysCtlKeyAddrLock(void)
{
    //
    // Lock the protected registers.
    //
    xHWREG(GCR_REGLOCK) = 0x00;
    
    return xHWREG(GCR_REGLOCK)&0x01;
}

//*****************************************************************************
//
//
//*****************************************************************************
unsigned long 
SysCtlResetSrcGet(void)
{
    //
    // Get reset source from last operation.
    //
    
    return xHWREG(GCR_RSTSRC);
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlResetSrcClear(unsigned long ulSrc)
{
    //
    // Check the arguments.
    //
    xASSERT((ulSrc == SYSCTL_RSTSRC_POR) ||
            (ulSrc == SYSCTL_RSTSRC_PAD) ||
            (ulSrc == SYSCTL_RSTSRC_WDG) ||
            (ulSrc == SYSCTL_RSTSRC_LVR) ||
            (ulSrc == SYSCTL_RSTSRC_BOD) ||
            (ulSrc == SYSCTL_RSTSRC_SYS) ||
            (ulSrc == SYSCTL_RSTSRC_CPU));
    //
    // Clear reset source from last operation.
    //
    
    xHWREG(GCR_RSTSRC) |= ulSrc;
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlBODEnable(xtBoolean bEnable)
{
    //
    // Enable BOD function or not.
    //
    SysCtlKeyAddrUnlock();
    if(bEnable)
    {
        xHWREG(GCR_BODCR) |= GCR_BODCR_BOD_EN;
    }
    else
    {
        xHWREG(GCR_BODCR) &= ~GCR_BODCR_BOD_EN;
    }
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlBODVoltSelect(unsigned char ulVoltage)
{
    //
    // Check the arguments.
    //
    xASSERT((ulVoltage == SYSCTL_BOD_2_2) ||
            (ulVoltage == SYSCTL_BOD_2_7) ||
            (ulVoltage == SYSCTL_BOD_3_7) ||
            (ulVoltage == SYSCTL_BOD_4_3));
    //
    // Select BOD threshold voltage.
    //
    SysCtlKeyAddrUnlock();
    xHWREG(GCR_BODCR) &= ~GCR_BODCR_BOD_VL_M;
    xHWREG(GCR_BODCR) |= ulVoltage;
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlBODLowPowerModeEnable(xtBoolean bEnable)
{
    //
    // Enable BOD low power mode or not.
    //
    SysCtlKeyAddrUnlock();
    if(bEnable)
    {
        xHWREG(GCR_BODCR) |= GCR_BODCR_BOD_LPM;
    }
    else
    {
        xHWREG(GCR_BODCR) &= ~GCR_BODCR_BOD_LPM;
    }
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlLowVoltRstEnable(xtBoolean bEnable)
{
    //
    // Enable Enable low voltage reset or not.
    //
    SysCtlKeyAddrUnlock();
    if(bEnable)
    {
        xHWREG(GCR_BODCR) |= GCR_BODCR_LVR_EN;
    }
    else
    {
        xHWREG(GCR_BODCR) &= ~GCR_BODCR_LVR_EN;
    }
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
xtBoolean
SysCtlBODStateGet(void)
{
    //
    // Get BOD state.
    //
    
    return (xHWREG(GCR_BODCR) & GCR_BODCR_BOD_OUT)>>6;
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlTempatureSensorEnable(xtBoolean bEnable)
{
    //
    // Enable Enable Tempature Sensor or not.
    //
    if(bEnable)
    {
        xHWREG(GCR_TEMPCR) |= GCR_TEMPCR_VTEMP_EN;
    }
    else
    {
        xHWREG(GCR_TEMPCR) &= ~GCR_TEMPCR_VTEMP_EN;
    }
}
//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlBODRstEnable(xtBoolean bEnable)
{
    //
    // Enable BOD reset function or interrupt function.
    //
    SysCtlKeyAddrUnlock();
    if(bEnable)
    {
        xHWREG(GCR_BODCR) |= GCR_BODCR_BOD_RSTEN;
    }
    else
    {
        xHWREG(GCR_BODCR) &= ~GCR_BODCR_BOD_RSTEN;
    }
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlIPClockDividerSet(unsigned long ulConfig)
{
    //
    // Check the arguments.
    //
    xASSERT((ulConfig & 0xFF)<=256);
    
    //
    // Set  this peripheral clock source
    //
    xHWREG(SYSCLK_CLKDIV) &= ~(SYSCTL_PERIPH_MASK_DIV(ulConfig));
    xHWREG(SYSCLK_CLKDIV) |= (SYSCTL_PERIPH_ENUM_CLK(ulConfig)-1);
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlFreqDividerOutputEnable(xtBoolean bEnable, unsigned char u8Divider)
{
    //
    // Check the arguments.
    //
    xASSERT(u8Divider<=15);
    
    //
    // Enable BOD reset function or interrupt function.
    //
    if(bEnable)
    {
        xHWREG(SYSCLK_FRQDIV) &= ~SYSCLK_FRQDIV_FSEL_M;
        xHWREG(SYSCLK_FRQDIV) |= u8Divider;
        xHWREG(SYSCLK_FRQDIV) |= SYSCLK_FRQDIV_FDIV_EN;
        SysCtlPeripheralEnable(SYSCTL_PERIPH_FDIV);
        
    }
    else
    {
        xHWREG(SYSCLK_FRQDIV) &= ~SYSCLK_FRQDIV_FDIV_EN;
        SysCtlPeripheralDisable(SYSCTL_PERIPH_FDIV);
    }
}
//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlPWRWUIntEnable(xtBoolean bEnable, xtBoolean bDelay)
{    
    //
    // Enable BOD reset function or interrupt function.
    //
    SysCtlKeyAddrUnlock();
    if(bEnable)
    {
        xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_PD_INT_EN;
        if(bDelay)
        {
            xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_WU_DLY;
        }
        else
        {
            xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_WU_DLY;
        }
    }
    else
    {
        xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_PD_INT_EN;
        xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_WU_DLY;
    }
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
void 
SysCtlPowerDownEnable(xtBoolean bEnable)
{    
    //
    // Enable or active power down function.
    //
    SysCtlKeyAddrUnlock();
    if(bEnable)
    {
        xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_PWR_DO_EN;
    }
    else
    {
        xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_PWR_DO_EN;
    }
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//
//*****************************************************************************
unsigned long 
SysCtlHClockGet(void)
{
    unsigned long  ulFreqout = 0, ulAHBDivider, ulPLLSrc, ulNF, ulNR, ulNO;
    unsigned long ulMap[4] = {1, 2, 2, 4};
    //
    // external 12MHz crystal clock.
    //
    if ((xHWREG(SYSCLK_CLKSEL0) & SYSCLK_CLKSEL0_HCLK_M) ==                    \
                                 SYSCLK_CLKSEL0_HCLK12M)
    {
        ulFreqout = s_ulExtClockMHz*1000000;  
    }
    //
    // PLL clock.
    //
    else if((xHWREG(SYSCLK_CLKSEL0) & SYSCLK_CLKSEL0_HCLK_M) ==                \
                                     SYSCLK_CLKSEL0_HCLKPLL)    
    {
        if((xHWREG(SYSCLK_PLLCON) & SYSCLK_PLLCON_PLL_SRC))
        {
            ulPLLSrc = 22000000;
        }
        else
        {
            ulPLLSrc = s_ulExtClockMHz*1000000;
        }
        if ((xHWREG(SYSCLK_PLLCON) & SYSCLK_PLLCON_PD))
        {
            ulFreqout = 0;
        }
        else
        {
            ulNF = (xHWREG(SYSCLK_PLLCON) & SYSCLK_PLLCON_FB_DV_M);
            ulNR = (xHWREG(SYSCLK_PLLCON) & SYSCLK_PLLCON_IN_DV_M) >>          \
                                           SYSCLK_PLLCON_IN_DV_S;
            ulNO = (xHWREG(SYSCLK_PLLCON) & SYSCLK_PLLCON_OUT_DV_M) >>          \
                                           SYSCLK_PLLCON_OUT_DV_S;
            ulFreqout =  ulPLLSrc*(ulNF+2)/(ulNR+2)/(ulMap[ulNO]);
        }
    }
    //
    // internal 10KHz oscillator clock.
    //
    else if((xHWREG(SYSCLK_CLKSEL0) & SYSCLK_CLKSEL0_HCLK_M) ==                \
                                     SYSCLK_CLKSEL0_HCLK10K)   
    {
        ulFreqout = 10000;
    }
    //
    // internal 22MHz oscillator clock.
    //
    else                              
    {
        ulFreqout = 22000000;
    
    }
    ulAHBDivider = (xHWREG(SYSCLK_CLKDIV) & SYSCLK_CLKDIV_HCLK_M) + 1 ;
    return (ulFreqout/ulAHBDivider);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SysCtlHClockSet(unsigned long ulConfig)
{

    s_ulExtClockMHz = ((ulConfig & SYSCTL_XTAL_MASK) >> 8);
    SysCtlKeyAddrUnlock();
    
    //
    // HLCK clock source is SYSCLK_CLKSEL0_HCLK12M
    //
    if(((ulConfig & 0xF0) >> 4) == SYSCLK_CLKSEL0_HCLK12M)
    {
        //
        // Check the arguments .
        //
        xASSERT((ulConfig & SYSCLK_PWRCON_XTL12M_EN)==0);
        
        xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_XTL12M_EN;
        SysCtlHClockSourceSet(SYSCTL_HLCK_S_EXT12M);
        //
        // Wait for the External 4~24 MHz High Speed Crystal Clock Source is stable
        //
        while(!(xHWREG(SYSCLK_CLKSTATUS) & SYSCLK_CLKSTATUS_XTL12M_STB));  
        SysCtlIPClockDividerSet(SYSCTL_PERIPH_HCLK_D |                        \
                               (((ulConfig & 0x0F000000) >> 24)+1));
        if((ulConfig & SYSCLK_PWRCON_OSC22M_EN)!=0)
        {
            xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_OSC22M_EN;
        }

        if((ulConfig & SYSCLK_PLLCON_PD)!=0)
        {
            xHWREG(SYSCLK_PLLCON) |= SYSCLK_PLLCON_PD;
        }
        
    }
    //
    // HLCK clock source is SYSCLK_CLKSEL0_HCLKPLL
    //
    else if(((ulConfig & 0xF0) >> 4) == SYSCLK_CLKSEL0_HCLKPLL)
    {
        //
        // Check the arguments .
        //
        xASSERT((ulConfig & SYSCLK_PLLCON_PD)==0);
        
        if((ulConfig & SYSCLK_PLLCON_PLL_SRC)==0)
        {
            //
            // Check the arguments .
            //
            xASSERT((ulConfig & SYSCLK_PWRCON_XTL12M_EN)==0);
            
            xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_XTL12M_EN;

            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_PLL_SRC;

            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_OE;

            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_PD;
            
            SysCtlDelay(1000);
            
            if((ulConfig & SYSCLK_PWRCON_OSC22M_EN)!=0)
            {
                xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_OSC22M_EN;
            }           
        }
        else 
        {
            //
            // Check the arguments .
            //
            xASSERT((ulConfig & SYSCLK_PWRCON_OSC22M_EN)==0);

            xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_OSC22M_EN;

            SysCtlHClockSourceSet(SYSCTL_HLCK_S_INT22M);

            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_FB_DV_M;
            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_IN_DV_M;
            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_OUT_DV_M;
            
            xHWREG(SYSCLK_PLLCON) |= (0x5E << SYSCLK_PLLCON_FB_DV_S);
            xHWREG(SYSCLK_PLLCON) |= (0x9 << SYSCLK_PLLCON_IN_DV_S);
            xHWREG(SYSCLK_PLLCON) |= (0x3 << SYSCLK_PLLCON_OUT_DV_S);
            
            xHWREG(SYSCLK_PLLCON) |= SYSCLK_PLLCON_PLL_SRC;

            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_OE;
            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_PD;
            xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_BP;
            SysCtlDelay(1000);
            
            if((ulConfig & SYSCLK_PWRCON_XTL12M_EN)!=0)
            {
                xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_XTL12M_EN;
            }
        }
        SysCtlHClockSourceSet(SYSCTL_HLCK_S_PLL);
        //
        // Wait for Internal PLL Clock Source is stable
        //
        while(!(xHWREG(SYSCLK_CLKSTATUS) & SYSCLK_CLKSTATUS_PLL_STB));
        SysCtlIPClockDividerSet(SYSCTL_PERIPH_HCLK_D |                        \
                               (((ulConfig & 0x0F000000) >> 24)+1));
    }
    //
    // HLCK clock source is SYSCLK_CLKSEL0_HCLK10K
    //
    else if(((ulConfig & 0xF0) >> 4) == SYSCLK_CLKSEL0_HCLK10K)
    {
        xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_OSC10K_EN;
        SysCtlHClockSourceSet(SYSCTL_HLCK_S_INT10K);
        //
        // Wait for Internal 10 kHz Low Speed Oscillator Clock Source is stable
        //
        while(!(xHWREG(SYSCLK_CLKSTATUS) & SYSCLK_CLKSTATUS_OSC10K_STB));
        SysCtlIPClockDividerSet(SYSCTL_PERIPH_HCLK_D |                        \
                               (((ulConfig & 0x0F000000) >> 24)+1));
        if((ulConfig & SYSCLK_PWRCON_OSC22M_EN)!=0)
        {
            xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_OSC22M_EN;
        }
        if((ulConfig & SYSCLK_PWRCON_XTL12M_EN)!=0)
        {
            xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_XTL12M_EN;
        }
        if((ulConfig & SYSCLK_PLLCON_PD)!=0)
        {
            xHWREG(SYSCLK_PLLCON) |= SYSCLK_PLLCON_PD;
        }
    }
    //
    // HLCK clock source is SYSCLK_PWRCON_OSC22M_EN
    //
    else 
    {
        //
        // Check the arguments .
        //
        xASSERT((ulConfig & SYSCLK_PWRCON_OSC22M_EN)==0);
        
        xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_OSC22M_EN;
        SysCtlHClockSourceSet(SYSCTL_HLCK_S_INT22M);
        //
        // Wait for Internal 22.1184 MHz High Speed Oscillator Clock Source is stable
        //
        while(!(xHWREG(SYSCLK_CLKSTATUS) & SYSCLK_CLKSTATUS_OSC22M_STB));
        SysCtlIPClockDividerSet(SYSCTL_PERIPH_HCLK_D |                        \
                               (((ulConfig & 0x0F000000) >> 24)+1));
        if((ulConfig & SYSCLK_PWRCON_XTL12M_EN)!=0)
        {
            xHWREG(SYSCLK_PWRCON) &= ~SYSCLK_PWRCON_XTL12M_EN;
        }
        if((ulConfig & SYSCLK_PLLCON_PD)!=0)
        {
            xHWREG(SYSCLK_PLLCON) |= SYSCLK_PLLCON_PD;
        }
    }
    SysCtlKeyAddrLock();
}