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00002
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00039
00040
00041 #ifndef __xSYSCTL_H__
00042 #define __xSYSCTL_H__
00043
00044
00045
00046
00047
00048
00049
00050 #ifdef __cplusplus
00051 extern "C"
00052 {
00053 #endif
00054
00055
00056
00059
00060
00061
00062
00063
00066
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00069
00070
00073
00074
00075
00076
00077
00140
00141
00142
00143 #define xSYSCTL_PERIPH_ACMP0 SYSCTL_PERIPH_ACMP
00144 #define xSYSCTL_PERIPH_ADC0 SYSCTL_PERIPH_ADC
00145 #define xSYSCTL_PERIPH_GPIOA SYSCTL_PERIPH_GPIO
00146 #define xSYSCTL_PERIPH_GPIOB SYSCTL_PERIPH_GPIO
00147 #define xSYSCTL_PERIPH_GPIOC SYSCTL_PERIPH_GPIO
00148 #define xSYSCTL_PERIPH_GPIOD SYSCTL_PERIPH_GPIO
00149 #define xSYSCTL_PERIPH_GPIOE SYSCTL_PERIPH_GPIO
00150 #define xSYSCTL_PERIPH_I2C0 SYSCTL_PERIPH_I2C0
00151 #define xSYSCTL_PERIPH_PWMA 0x40105030
00152 #define xSYSCTL_PERIPH_PWMB 0x401050C0
00153 #define xSYSCTL_PERIPH_SPI0 SYSCTL_PERIPH_SPI0
00154 #define xSYSCTL_PERIPH_SPI1 SYSCTL_PERIPH_SPI1
00155 #define xSYSCTL_PERIPH_TIMER0 SYSCTL_PERIPH_TMR0
00156 #define xSYSCTL_PERIPH_TIMER1 SYSCTL_PERIPH_TMR1
00157 #define xSYSCTL_PERIPH_TIMER2 SYSCTL_PERIPH_TMR2
00158 #define xSYSCTL_PERIPH_TIMER3 SYSCTL_PERIPH_TMR3
00159 #define xSYSCTL_PERIPH_UART0 SYSCTL_PERIPH_UART0
00160 #define xSYSCTL_PERIPH_UART1 SYSCTL_PERIPH_UART1
00161 #define xSYSCTL_PERIPH_WDOG SYSCTL_PERIPH_WDT
00162
00163
00164
00166
00167
00168
00169
00170
00222
00223
00224
00225 #define xSYSCTL_OSC_MAIN (SYSCTL_OSC_MAIN | SYSCTL_PLL_MAIN)
00226 #define xSYSCTL_OSC_INT (SYSCTL_OSC_INT | SYSCTL_PLL_INT)
00227 #define xSYSCTL_OSC_INTSL SYSCTL_OSC_INTSL
00228 #define xSYSCTL_OSC_EXTSL SYSCTL_OSC_EXTSL
00229
00230
00232
00233 #define xSYSCTL_XTAL_4MHZ SYSCTL_XTAL_4MHZ
00234 #define xSYSCTL_XTAL_5MHZ SYSCTL_XTAL_5MHZ
00235 #define xSYSCTL_XTAL_6MHZ SYSCTL_XTAL_6MHZ
00236 #define xSYSCTL_XTAL_7MHZ SYSCTL_XTAL_7MHZ
00237 #define xSYSCTL_XTAL_8MHZ SYSCTL_XTAL_8MHZ
00238 #define xSYSCTL_XTAL_9MHZ SYSCTL_XTAL_9MHZ
00239 #define xSYSCTL_XTAL_10MHZ SYSCTL_XTAL_10MHZ
00240 #define xSYSCTL_XTAL_11MHZ SYSCTL_XTAL_11MHZ
00241 #define xSYSCTL_XTAL_12MHZ SYSCTL_XTAL_12MHZ
00242 #define xSYSCTL_XTAL_13MHZ SYSCTL_XTAL_13MHZ
00243 #define xSYSCTL_XTAL_14MHZ SYSCTL_XTAL_14MHZ
00244 #define xSYSCTL_XTAL_15MHZ SYSCTL_XTAL_15MHZ
00245 #define xSYSCTL_XTAL_16MHZ SYSCTL_XTAL_16MHZ
00246 #define xSYSCTL_XTAL_17MHZ SYSCTL_XTAL_17MHZ
00247 #define xSYSCTL_XTAL_18MHZ SYSCTL_XTAL_18MHZ
00248 #define xSYSCTL_XTAL_19MHZ SYSCTL_XTAL_19MHZ
00249 #define xSYSCTL_XTAL_20MHZ SYSCTL_XTAL_20MHZ
00250 #define xSYSCTL_XTAL_21MHZ SYSCTL_XTAL_21MHZ
00251 #define xSYSCTL_XTAL_22MHZ SYSCTL_XTAL_22MHZ
00252 #define xSYSCTL_XTAL_23MHZ SYSCTL_XTAL_23MHZ
00253 #define xSYSCTL_XTAL_24MHZ SYSCTL_XTAL_24MHZ
00254
00255
00257
00258 #define xSYSCTL_INT_22MHZ 0x00000000
00259
00260
00262
00263 #define xSYSCTL_INTSL_10KHZ 0x00000000
00264
00265
00267
00268 #define xSYSCTL_INT_OSC_DIS 0x00000004
00269
00270
00272
00273 #define xSYSCTL_MAIN_OSC_DIS 0x00000001
00274
00275
00277
00278 #define xSYSCTL_PLL_PWRDN 0x00010000
00279
00280
00281
00283
00284
00285
00286
00287
00319
00320
00321
00322
00324
00325 #define xSYSCTL_WDT0_EXTSL 0x00000300
00326
00327
00329
00330 #define xSYSCTL_WDT0_HCLK_2048 0x00000302
00331
00332
00334
00335 #define xSYSCTL_WDT0_INTSL 0x00000303
00336
00337
00339
00340 #define xSYSCTL_ADC0_MAIN 0x01021000
00341
00342
00344
00345 #define xSYSCTL_ADC0_PLL 0x01021001
00346
00347
00349
00350 #define xSYSCTL_ADC0_HCLK 0x01021002
00351
00352
00354
00355 #define xSYSCTL_ADC0_INT 0x01021003
00356
00357
00359
00360 #define xSYSCTL_TIMER0_MAIN 0x00080700
00361
00362
00364
00365 #define xSYSCTL_TIMER0_HCLK 0x00080702
00366
00367
00369
00370 #define xSYSCTL_TIMER0_INT 0x00080707
00371
00372
00374
00375 #define xSYSCTL_TIMER1_MAIN 0x000C0700
00376
00377
00379
00380 #define xSYSCTL_TIMER1_HCLK 0x000C0702
00381
00382
00384
00385 #define xSYSCTL_TIMER1_INT 0x000C0707
00386
00387
00389
00390 #define xSYSCTL_TIMER2_MAIN 0x00100700
00391
00392
00394
00395 #define xSYSCTL_TIMER2_HCLK 0x00100702
00396
00397
00399
00400 #define xSYSCTL_TIMER2_INT 0x00100707
00401
00402
00404
00405 #define xSYSCTL_TIMER3_MAIN 0x00140700
00406
00407
00409
00410 #define xSYSCTL_TIMER3_HCLK 0x00140702
00411
00412
00414
00415 #define xSYSCTL_TIMER3_INT 0x00140707
00416
00417
00419
00420 #define xSYSCTL_UART0_MAIN 0x01180800
00421
00422
00424
00425 #define xSYSCTL_UART0_PLL 0x01180801
00426
00427
00429
00430 #define xSYSCTL_UART0_INT 0x01180803
00431
00432
00434
00435 #define xSYSCTL_UART1_MAIN 0x01180800
00436
00437
00439
00440 #define xSYSCTL_UART1_PLL 0x01180801
00441
00442
00444
00445 #define xSYSCTL_UART1_INT 0x01180803
00446
00447
00449
00450 #define xSYSCTL_PWMA_MAIN 0x001C0300
00451
00452
00454
00455 #define xSYSCTL_PWMA_HCLK 0x001C0302
00456
00457
00459
00460 #define xSYSCTL_PWMA_INT 0x001C0303
00461
00462
00464
00465 #define xSYSCTL_FRQDIV_MAIN 0x10020300
00466
00467
00469
00470 #define xSYSCTL_FRQDIV_HCLK 0x10020302
00471
00472
00474
00475 #define xSYSCTL_FRQDIV_INT 0x10020303
00476
00477
00479
00480 #define xSYSCTL_PWMB_MAIN 0x10040300
00481
00482
00484
00485 #define xSYSCTL_PWMB_HCLK 0x10040302
00486
00487
00489
00490 #define xSYSCTL_PWMB_INT 0x10040303
00491
00492
00493
00494
00496
00497
00498
00499
00500
00561
00562
00563 #define PWMA PWMA
00564 #define PWMB PWMB
00565 #define TIMER0 TIMER0
00566 #define TIMER1 TIMER1
00567 #define TIMER2 TIMER2
00568 #define TIMER3 TIMER3
00569 #define UART0 UART0
00570 #define UART1 UART1
00571 #define WDT0 WDT0
00572
00573
00575
00576 #define INT INT
00577
00578
00580
00581 #define HCLK HCLK
00582
00583
00585
00586 #define HCLK_2048 HCLK_2048
00587
00588
00590
00591 #define EXTSL EXTSL
00592
00593
00595
00596 #define INTSL INTSL
00597
00598
00600
00601 #define MAIN MAIN
00602
00603
00605
00606 #define PLL PLL
00607
00608
00610
00611 #define PLL_2 PLL_2
00612
00613
00615
00616 #define EXTTRG EXTTRG
00617
00618
00619
00621
00622
00623
00624
00625
00664
00665
00666
00667
00668
00683
00684
00685 #define xSysCtlPeripheralReset(ulPeripheralID) \
00686 SysCtlPeripheralReset(ulPeripheralID)
00687
00688
00689
00703
00704
00705 #define xSysCtlPeripheralEnable(ulPeripheralID) \
00706 SysCtlPeripheralEnable(ulPeripheralID)
00707
00708 extern void xSysCtlPeripheralEnable2(unsigned long ulPeripheralBase);
00709 extern void xSysCtlPeripheralDisable2(unsigned long ulPeripheralBase);
00710 extern void xSysCtlPeripheralReset2(unsigned long ulPeripheralBase);
00711 extern void xSysCtlPeripheralClockSourceSet(unsigned long ulPeripheralSrc,
00712 unsigned long ulDivide);
00713 extern unsigned long xSysCtlPeripheralIntNumGet(unsigned long ulPeripheralBase);
00714
00715
00716
00757
00758
00759 #define xSysCtlPeripheralClockSourceSet2(ePeripheral, eSrc, ulDivide) \
00760 SysCtlIPClockSourceSetConvert(ePeripheral, eSrc, ulDivide)
00761
00762
00763
00776
00777
00778 #define xSysCtlPeripheralDisable(ulPeripheralID) \
00779 SysCtlPeripheralDisable(ulPeripheralID)
00780
00781 extern void xSysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig);
00782
00783
00784
00798
00799
00800 #define xSysCtlClockGet() \
00801 SysCtlHClockGet()
00802
00803
00804
00816
00817
00818 #define xSysCtlDelay(ulCount) \
00819 SysCtlDelay(ulCount)
00820
00821
00822
00832
00833
00834 #define xSysCtlReset() \
00835 SysCtlReset()
00836
00837
00838
00845
00846
00847 #define xSysCtlSleep() \
00848 SysCtlSleep()
00849
00850
00851
00853
00854
00855
00856
00857
00859
00860
00861
00862
00863
00866
00867
00868
00869
00870
00875
00876
00877
00878
00880
00881 #define SYSCTL_PERIPH_ISP 0x00000004
00882
00883
00885
00886 #define SYSCTL_PERIPH_WDT 0x00004001
00887
00888
00890
00891 #define SYSCTL_PERIPH_GPIO 0x70020000
00892
00893
00895
00896 #define SYSCTL_PERIPH_TMR0 0x70044004
00897
00898
00900
00901 #define SYSCTL_PERIPH_TMR1 0x70084008
00902
00903
00905
00906 #define SYSCTL_PERIPH_TMR2 0x70104010
00907
00908
00910
00911 #define SYSCTL_PERIPH_TMR3 0x70204020
00912
00913
00915
00916 #define SYSCTL_PERIPH_FDIV 0x00004040
00917
00918
00920
00921 #define SYSCTL_PERIPH_I2C0 0x68024801
00922
00923
00925
00926 #define SYSCTL_PERIPH_SPI0 0x68104810
00927
00928
00930
00931 #define SYSCTL_PERIPH_SPI1 0x68204820
00932
00933
00935
00936 #define SYSCTL_PERIPH_UART0 0x40015001
00937
00938
00940
00941 #define SYSCTL_PERIPH_UART1 0x40025002
00942
00943
00945
00946 #define SYSCTL_PERIPH_PWM01 0x40105010
00947
00948
00950
00951 #define SYSCTL_PERIPH_PWM23 0x40105020
00952
00953
00955
00956 #define SYSCTL_PERIPH_PWM45 0x40205040
00957
00958
00960
00961 #define SYSCTL_PERIPH_PWM67 0x40205080
00962
00963
00965
00966 #define SYSCTL_PERIPH_ADC 0x48105810
00967
00968
00970
00971 #define SYSCTL_PERIPH_ACMP 0x40405840
00972
00973
00974
00976
00977
00978
00979
00980
00985
00986
00987
00988
00990
00991 #define SYSCTL_PERIPH_WDG_EXTSL 0x00000300
00992
00993
00995
00996 #define SYSCTL_PERIPH_WDG_S_HCLK_2048 \
00997 0x00000302
00998
00999
01001
01002 #define SYSCTL_PERIPH_WDG_S_INT10K \
01003 0x00000303
01004
01005
01007
01008 #define SYSCTL_PERIPH_ADC_S_EXT12M \
01009 0x00020300
01010
01011
01013
01014 #define SYSCTL_PERIPH_ADC_S_PLL \
01015 0x00020301
01016
01017
01019
01020 #define SYSCTL_PERIPH_ADC_S_HCLK \
01021 0x00020302
01022
01023
01025
01026 #define SYSCTL_PERIPH_ADC_S_INT22M \
01027 0x00020303
01028
01029
01031
01032 #define SYSCTL_PERIPH_TMR0_S_EXT12M \
01033 0x00080700
01034
01036
01037 #define SYSCTL_PERIPH_TMR0_S_HCLK \
01038 0x00080702
01039
01040
01042
01043 #define SYSCTL_PERIPH_TMR0_S_INT22M \
01044 0x00080707
01045
01046
01048
01049 #define SYSCTL_PERIPH_TMR1_S_EXT12M \
01050 0x000C0700
01051
01052
01054
01055 #define SYSCTL_PERIPH_TMR1_S_HCLK \
01056 0x000C0702
01057
01058
01060
01061 #define SYSCTL_PERIPH_TMR1_S_INT22M \
01062 0x000C0707
01063
01064
01066
01067 #define SYSCTL_PERIPH_TMR2_S_EXT12M \
01068 0x00100700
01069
01070
01072
01073 #define SYSCTL_PERIPH_TMR2_S_HCLK \
01074 0x00100702
01075
01076
01078
01079 #define SYSCTL_PERIPH_TMR2_S_INT22M \
01080 0x00100707
01081
01082
01084
01085 #define SYSCTL_PERIPH_TMR3_S_EXT12M \
01086 0x00140700
01087
01088
01090
01091 #define SYSCTL_PERIPH_TMR3_S_HCLK \
01092 0x00140702
01093
01094
01096
01097 #define SYSCTL_PERIPH_TMR3_S_INT22M \
01098 0x00140707
01099
01100
01102
01103 #define SYSCTL_PERIPH_UART_S_EXT12M \
01104 0x00180300
01105
01106
01108
01109 #define SYSCTL_PERIPH_UART_S_PLL \
01110 0x00180301
01111
01112
01114
01115 #define SYSCTL_PERIPH_UART_S_INT22M \
01116 0x00180303
01117
01118
01120
01121 #define SYSCTL_PERIPH_PWM01_S_EXT12M \
01122 0x001C0300
01123
01124
01126
01127 #define SYSCTL_PERIPH_PWM01_S_HCLK \
01128 0x001C0302
01129
01130
01132
01133 #define SYSCTL_PERIPH_PWM01_S_INT22M \
01134 0x001C0303
01135
01136
01138
01139 #define SYSCTL_PERIPH_PWM23_S_EXT12M \
01140 0x001E0300
01141
01142
01144
01145 #define SYSCTL_PERIPH_PWM23_S_HCLK \
01146 0x001E0302
01147
01148
01150
01151 #define SYSCTL_PERIPH_PWM23_S_INT22M \
01152 0x001E0303
01153
01154
01156
01157 #define SYSCTL_PERIPH_FRQDIV_S_EXT12M \
01158 0x10020300
01159
01160
01162
01163 #define SYSCTL_PERIPH_FRQDIV_S_HCLK \
01164 0x10020302
01165
01166
01168
01169 #define SYSCTL_PERIPH_FRQDIV_S_INT22M \
01170 0x10020303
01171
01172
01174
01175 #define SYSCTL_PERIPH_PWM45_S_EXT12M \
01176 0x10040300
01177
01178
01180
01181 #define SYSCTL_PERIPH_PWM45_S_HCLK \
01182 0x10040302
01183
01184
01186
01187 #define SYSCTL_PERIPH_PWM45_S_INT22M \
01188 0x10040303
01189
01190
01192
01193 #define SYSCTL_PERIPH_PWM67_S_EXT12M \
01194 0x10060300
01195
01196
01198
01199 #define SYSCTL_PERIPH_PWM67_S_HCLK \
01200 0x10060302
01201
01202
01204
01205 #define SYSCTL_PERIPH_PWM67_S_INT22M \
01206 0x10060303
01207
01208
01209
01211
01212
01213
01214
01215
01220
01221
01222
01223
01225
01226 #define SYSCTL_HLCK_S_EXT12M 0x00000000
01227
01228
01230
01231 #define SYSCTL_HLCK_S_PLL 0x00000002
01232
01233
01235
01236 #define SYSCTL_HLCK_S_INT10K 0x00000003
01237
01238
01240
01241 #define SYSCTL_HLCK_S_INT22M 0x00000007
01242
01243
01244
01246
01247
01248
01249
01250
01255
01256
01257
01258
01260
01261 #define SYSCTL_STCLK_S_EXT12M 0x00000000
01262
01263
01265
01266 #define SYSCTL_STCLK_S_EXT12M_2 0x00000010
01267
01268
01270
01271 #define SYSCTL_STCLK_S_HCLK_2 0x00000018
01272
01273
01275
01276 #define SYSCTL_STCLK_S_INT22M_2 0x00000038
01277
01278
01279
01281
01282
01283
01284
01285
01290
01291
01292
01293
01295
01296 #define SYSCTL_RSTSRC_POR 0x00000001
01297
01298
01300
01301 #define SYSCTL_RSTSRC_PAD 0x00000002
01302
01303
01305
01306 #define SYSCTL_RSTSRC_WDG 0x00000004
01307
01308
01310
01311 #define SYSCTL_RSTSRC_LVR 0x00000008
01312
01313
01315
01316 #define SYSCTL_RSTSRC_BOD 0x00000010
01317
01318
01320
01321 #define SYSCTL_RSTSRC_SYS 0x00000020
01322
01323
01325
01326 #define SYSCTL_RSTSRC_CPU 0x00000080
01327
01328
01329
01331
01332
01333
01334
01335
01340
01341
01342
01343
01345
01346 #define SYSCTL_BOD_2_2 0x00000000
01347
01348
01350
01351 #define SYSCTL_BOD_2_7 0x00000002
01352
01353
01355
01356 #define SYSCTL_BOD_3_7 0x00000004
01357
01358
01360
01361 #define SYSCTL_BOD_4_3 0x00000006
01362
01363
01364
01366
01367
01368
01369
01370
01375
01376
01377
01378
01380
01381 #define SYSCTL_PERIPH_HCLK_D 0x00000000
01382
01383
01385
01386 #define SYSCTL_PERIPH_UART_D 0x00080800
01387
01388
01390
01391 #define SYSCTL_PERIPH_ADC_D 0x00101000
01392
01393
01394
01396
01397
01398
01399
01400
01405
01406
01407
01408
01410
01411 #define SYSCTL_SYSDIV_1 0x00000000
01412
01413
01415
01416 #define SYSCTL_SYSDIV_2 0x01000000
01417
01418
01420
01421 #define SYSCTL_SYSDIV_3 0x02000000
01422
01423
01425
01426 #define SYSCTL_SYSDIV_4 0x03000000
01427
01428
01430
01431 #define SYSCTL_SYSDIV_5 0x04000000
01432
01433
01435
01436 #define SYSCTL_SYSDIV_6 0x05000000
01437
01438
01440
01441 #define SYSCTL_SYSDIV_7 0x06000000
01442
01443
01445
01446 #define SYSCTL_SYSDIV_8 0x07000000
01447
01448
01450
01451 #define SYSCTL_SYSDIV_9 0x08000000
01452
01453
01455
01456 #define SYSCTL_SYSDIV_10 0x09000000
01457
01458
01460
01461 #define SYSCTL_SYSDIV_11 0x0A000000
01462
01463
01465
01466 #define SYSCTL_SYSDIV_12 0x0B000000
01467
01468
01470
01471 #define SYSCTL_SYSDIV_13 0x0C000000
01472
01473
01475
01476 #define SYSCTL_SYSDIV_14 0x0D000000
01477
01478
01480
01481 #define SYSCTL_SYSDIV_15 0x0E000000
01482
01483
01485
01486 #define SYSCTL_SYSDIV_16 0x0F000000
01487
01488
01490
01491 #define SYSCTL_INT_OSC_DIS 0x00000004
01492
01493
01495
01496 #define SYSCTL_MAIN_OSC_DIS 0x00000001
01497
01498
01500
01501 #define SYSCTL_PLL_PWRDN 0x00010000
01502
01503
01505
01506 #define SYSCTL_OSC_MAIN 0x00000000
01507
01508
01510
01511 #define SYSCTL_OSC_EXTSL 0x00000010
01512
01513
01515
01516 #define SYSCTL_OSC_PLL 0x00000020
01517
01518
01520
01521 #define SYSCTL_OSC_INT 0x00000040
01522
01523
01525
01526 #define SYSCTL_OSC_INTSL 0x00000030
01527
01528
01530
01531 #define SYSCTL_OSCSRC_M 0x00080070
01532
01533
01535
01536 #define SYSCTL_PLL_MAIN 0x00000000
01537
01538
01540
01541 #define SYSCTL_PLL_INT 0x00080000
01542
01543
01545
01546 #define SYSCTL_XTAL_MASK 0x0000FF00
01547
01548
01550
01551 #define SYSCTL_XTAL_4MHZ 0x00000400
01552
01553
01555
01556 #define SYSCTL_XTAL_5MHZ 0x00000500
01557
01558
01560
01561 #define SYSCTL_XTAL_6MHZ 0x00000600
01562
01563
01565
01566 #define SYSCTL_XTAL_7MHZ 0x00000700
01567
01568
01570
01571 #define SYSCTL_XTAL_8MHZ 0x00000800
01572
01573
01575
01576 #define SYSCTL_XTAL_9MHZ 0x00000900
01577
01578
01580
01581 #define SYSCTL_XTAL_10MHZ 0x00000A00
01582
01583
01585
01586 #define SYSCTL_XTAL_11MHZ 0x00000B00
01587
01588
01590
01591 #define SYSCTL_XTAL_12MHZ 0x00000C00
01592
01593
01595
01596 #define SYSCTL_XTAL_13MHZ 0x00000D00
01597
01598
01600
01601 #define SYSCTL_XTAL_14MHZ 0x00000E00
01602
01603
01605
01606 #define SYSCTL_XTAL_15MHZ 0x00000F00
01607
01608
01610
01611 #define SYSCTL_XTAL_16MHZ 0x00001000
01612
01613
01615
01616 #define SYSCTL_XTAL_17MHZ 0x00001100
01617
01618
01620
01621 #define SYSCTL_XTAL_18MHZ 0x00001200
01622
01623
01625
01626 #define SYSCTL_XTAL_19MHZ 0x00001300
01627
01628
01630
01631 #define SYSCTL_XTAL_20MHZ 0x00001400
01632
01633
01635
01636 #define SYSCTL_XTAL_21MHZ 0x00001500
01637
01638
01640
01641 #define SYSCTL_XTAL_22MHZ 0x00001600
01642
01643
01645
01646 #define SYSCTL_XTAL_23MHZ 0x00001700
01647
01648
01650
01651 #define SYSCTL_XTAL_24MHZ 0x00001800
01652
01653
01654
01656
01657
01658
01659
01660
01663
01664
01665 #define SysCtlIPClockSourceSetConvert(ulPeripheral, ulSrc, ulDivide) \
01666 xSysCtlPeripheralClockSourceSet(xSYSCTL_##ulPeripheral##_##ulSrc, \
01667 ulDivide);
01668
01669 extern void SysCtlDelay(unsigned long ulCount);
01670
01671 extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
01672 extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
01673 extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
01674 extern void SysCtlPeripheralClockSourceSet(unsigned long ulPeripheralSrc);
01675 extern void SysCtlHClockSourceSet(unsigned long ulHclkSrcSel);
01676 extern void SysCtlSysTickSourceSet(unsigned long ulStclkSrcSel);
01677
01678 extern void SysCtlCPUReset(void);
01679 extern void SysCtlChipReset(void);
01680 extern void SysCtlSleep(void);
01681 extern void SysCtlReset(void);
01682 extern void SysCtlDeepSleep(void);
01683
01684 extern xtBoolean SysCtlKeyAddrUnlock(void);
01685 extern xtBoolean SysCtlKeyAddrLock(void);
01686
01687 extern unsigned long SysCtlResetSrcGet(void);
01688 extern void SysCtlResetSrcClear(unsigned long ulSrc);
01689
01690 extern void SysCtlBODEnable(xtBoolean bEnable);
01691 extern void SysCtlBODVoltSelect(unsigned char ulVoltage);
01692 extern void SysCtlBODLowPowerModeEnable(xtBoolean bEnable);
01693 extern void SysCtlLowVoltRstEnable(xtBoolean bEnable);
01694 extern xtBoolean SysCtlBODStateGet(void);
01695 extern void SysCtlBODRstEnable(xtBoolean bEnable);
01696 extern void SysCtlTempatureSensorEnable(xtBoolean bEnable);
01697
01698 extern void SysCtlIPClockDividerSet(unsigned long ulConfig);
01699 extern void SysCtlFreqDividerOutputEnable(xtBoolean bEnable, unsigned char u8Divider);
01700 extern void SysCtlPWRWUIntEnable(xtBoolean bEnable, xtBoolean bDelay);
01701 extern void SysCtlPowerDownEnable(xtBoolean bEnable);
01702 extern void SysCtlPowerDownWaitCPUSet(xtBoolean bEnable);
01703 extern unsigned long SysCtlHClockGet(void);
01704 extern void SysCtlHClockSet(unsigned long ulConfig);
01705
01706
01707
01709
01710
01711
01712
01713
01715
01716
01717
01718
01719
01721
01722
01723
01724
01725
01727
01728
01729
01730
01731
01732
01733
01734
01735
01736 #ifdef __cplusplus
01737 }
01738 #endif
01739
01740 #endif // __xSYSCTL_H__
01741